Embodiments of the present invention relate generally to integrated circuit chips, and more specifically, to eliminating poor reveal of through silicon vias (TSVs).
TSVs are generally vertical connections etched through a silicon wafer and filled with metal. With TSVs, two or more vertically stacked chips (or dies) can be joined by vertical interconnects running through the stack and functioning as components of an integrated circuit. Stacking chips in comparison to wire bonding, reduces inductive loses which increases speed of data exchange. Since TSVs have shorter interconnects between the dies, there will be reduced power consumption caused by long horizontal wiring. As a result, TSVs allow much higher input/output density than wire bonding, which consumes much more space.
In this manner, TSVs allow multiple integrated circuit chips to be stacked together, allowing greater amounts of information to be passed between the chips. For example, integrated circuit chips and memory devices which typically reside side-by-side on a silicon wafer, can be stacked on top of another with the advent of the TSVs. Stacking the integrated circuit chips with the memory devices will dramatically reduce the size of the overall chip package and boost speeds at which data flows among the functions on the chip.
After formation of TSVs in a silicon wafer, a back side grind operation is typically performed on the back side of the wafer to reveal the TSVs. Poor reveal of the TSVs can arise due to the vias not being etched deep enough during their formation. That is, if the trenches of the TSVs are not etched deep enough during formation, then when the back side grind operation is performed on the wafer, the TSVs will not be revealed. Poor reveal of TSVs that are not etched enough are problematic because a vertical electrical connection will not be attained. The impact of poor reveal of the TSVs will depend on how much of the wafer has the poor reveal. Typically, poor reveal of TSVs will appear on the edge of the wafer and progress towards the center of the wafer. If the poor reveal is within a wafer pickable area, then the wafer may need to be scrapped.